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PLA with Internally ORed Functions

IP.com Disclosure Number: IPCOM000051403D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Delahanty, RJ: AUTHOR

Abstract

A method is provided for ORing the outputs of two Programmed Logic Arrays (PLAs) on the same chip while obtaining the results in the same PLA cycle as the rest of the outputs. This is accomplished by ORing the outputs internally before latching.

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PLA with Internally ORed Functions

A method is provided for ORing the outputs of two Programmed Logic Arrays (PLAs) on the same chip while obtaining the results in the same PLA cycle as the rest of the outputs. This is accomplished by ORing the outputs internally before latching.

Frequently in synchronous PLA-macro designs, the outputs from the OR array set a "master" latch on one half of the PLA cycle and transfer the information to a "slave" latch on the other. To OR the signals only after the slave latches have been set would delay the availability of the ORed signal to the next cycle. This is true whether the ORing (of the slave latch outputs) is accomplished with another PLA or with a random logic block. In the latter case, the delay of the ORed signal by the random logic block could be too great to allow use of this signal on the next PLA cycle.

By inserting the random logic block between the raw (i.e., unlatched) PLA outputs and the master latch, the OR function and setting its result in the latches can be accomplished in the same cycle as the rest of the outputs. Fig. 1 shows such an arrangement, and Fig. 2 shows the corresponding timing.

Macro chip 10 includes PLAs 12 and 14. Inputs 16-18 to 12 result in output A, and inputs 20-22 to PLA 14 result in output B. Field effect transistors PLA (FETs) 24, 26, 28 provide an inverted OR (NOR) function A + B which is clocked at latch 30 to the above-described master/slave latch 32, 34.

By operation of the latch,...