Browse Prior Art Database

Storage Array with Bad Bit Bypass

IP.com Disclosure Number: IPCOM000051404D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Wu, WW: AUTHOR

Abstract

A memory word line having a bad storage cell is disabled and a spare word line is activated by a programmable logic array that is personalized to decode the address of a disabled word line and to supply an accessing current to the substituted line.

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Storage Array with Bad Bit Bypass

A memory word line having a bad storage cell is disabled and a spare word line is activated by a programmable logic array that is personalized to decode the address of a disabled word line and to supply an accessing current to the substituted line.

The drawing shows a conventional storage array having bit lines 2 in columns, word lines 3, 3' in rows, and diodes or other storage elements 4, 4' at the crossover points of the row and column lines. The storage elements 3 are selectively open-circuited to form a data pattern. Current applied to an addressed row line flows in each column line where there is a connecting diode and does not flow in a column line where the diode has been removed. Bit line detector circuits (not shown) respond to the presence or absence of the bit line currents to signal the data word represented by the diode pattern of the addressed row line.

A conventional address decoder circuit 6 drives one of the row lines in response to address signals at terminals 7. A line 8 supplies an address bit to the decoder, and an inverter 9 and a line 10 supply the complement of the address bit to the decoder. In a conventional storage array of this type, some of the storage cells may be defective, and spare row lines 11 and storage elements 12 are provided as replacements.

The memory includes a column line 14 that crosses each of the normal row lines. These crossovers are constructed to permit a laser weld operation that s...