Browse Prior Art Database

Reset Signal Generator for a Processor

IP.com Disclosure Number: IPCOM000051416D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Anderson, GA: AUTHOR [+2]

Abstract

A reset signal for a microprocessor is typically required to occur afte a fixed delay interval has occurred from the time power is applied. The reset signal generator described below assures that an adequate delay interval will occur even in short-term power-loss situations.

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Reset Signal Generator for a Processor

A reset signal for a microprocessor is typically required to occur afte a fixed delay interval has occurred from the time power is applied. The reset signal generator described below assures that an adequate delay interval will occur even in short-term power-loss situations.

Reset signal generators typically rely on a timing capacitor to establish a delay interval. However, in temporary power loss situations, the voltage profile for the timing capacitor may depart from the desired profile because of retained charge. With the circuit of the figure, a consistent delay interval is provided for a wide range of conditions by assuring that the timing capacitor C is discharged before a timing interval begins.

The charging path for the capacitor C includes the resistor R5 which serves to define the slope of a ramp-like timing signal. The timing signal is supplied to a bi-stable trigger circuit 12 that includes a basic Schmitt trigger section made up of transistors T4 and T6, resistors R7 and R8, and diode D7. The base of transistor T4 serves as the input point for the timing signal, and the collector of transistor T6 provides the output for the Schmitt trigger section having a waveform with two stable states. Transistors T5 and T7 cooperate with resistors R10 and R1 to provide a current source for the Schmitt trigger section. The circuit including transistors T8-T11 diodes D3-D6, and resistors R12-R16 form a voltage-sensitive buffer for the output at the collector terminal of transistor T6 and provide a reset signal for a processor at the collector terminal of transistor T11.

A detection circuit 10 serves to discharge the capacitor C in situations where the power supply voltage falls below a predefined detection level that is slightly below the nominal level (assumed to be 5 volts). The detection voltage level is defined by a resistor divider that includes diodes D1 and D2 and the resistors R1 and R2. The voltage across the resistor R2 is supplied to a transistor T1 that is connected in series with a load resi...