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Testing Tristate Off Chip Drivers in FET Designs

IP.com Disclosure Number: IPCOM000051422D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Puri, PP: AUTHOR [+2]

Abstract

A technique is disclosed for testing a tristate off-chip driver (OCD) circuit such as is shown in Fig. 1. The testing technique employs an off-chip test load connected between the tester and the output terminal of the circuit, shown in Fig. 2. The test load is a resistor R(L) and diode V(D) connected between a tester-supplied voltage V(L) and the output node of the OCD circuit.

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Testing Tristate Off Chip Drivers in FET Designs

A technique is disclosed for testing a tristate off-chip driver (OCD) circuit such as is shown in Fig. 1. The testing technique employs an off-chip test load connected between the tester and the output terminal of the circuit, shown in Fig.
2. The test load is a resistor R(L) and diode V(D) connected between a tester- supplied voltage V(L) and the output node of the OCD circuit.

When the OCD logic is enabled by E being down, the OCD output provides a logic 0 state when FET 2 conducts and logic 1 state when FET 1 conducts, which are testable as in a conventional OCD. When the high state is selected by the input E being up, the OCD output provides a distinct voltage different from the logic 0 and logic 1 voltages. This is achieved by the resistor R(L) and diode V(D) conducting a DC current into the OCD output during the output logic 0 state. The output logic 1 state is determined when the input E is up since no DC current can flow into V(L) due to the reverse biased diode V(D). Thus, the addition of the load circuit to the tester enables reliable testing of a tristate OCD circuit.

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