Browse Prior Art Database

Error Correcting Code for Multiple Package Error Detection

IP.com Disclosure Number: IPCOM000051428D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR

Abstract

By proper mapping of error correcting bits, errors in support circuits can be detected.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Error Correcting Code for Multiple Package Error Detection

By proper mapping of error correcting bits, errors in support circuits can be detected.

For instance, the single error correcting and double error detecting code (ECC), whose parity check matrix is shown in the figure, can be used to detect failures. Assume that all 40 bits of a code word are distributed 4 bits each on 10 array modules of an array card.

With the receiver-driver circuit (RD) modules of the array card packaged with respect to the array bits as shown in Table I, a failure in an RD module would result in 2- or 3-bit errors. With interface driver circuit (ID) modules for array selects and register selects of the array care packaged as shown in Table II and Table III, a circuit failure would result in 2-, 3-, or 5-bit errors depending on the specific ID module.

To detect the errors caused by the RD and ID failures, the ECC bits are mapped into the array modules as shown in Table IV. The mapping provides in addition to the normal single error correction and double error detection, the detection of package errors caused by a failure of the following modules: a) RD modules,

b) ID modules for array selects, and

c) ID modules for register selects.

See Original (Table I, Table II, Table III and Table IV).

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]