Browse Prior Art Database

Avalanche Erasure Current Control Circuit for EAROM Array

IP.com Disclosure Number: IPCOM000051440D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Hoffman, CR: AUTHOR [+2]

Abstract

This article describes an FET circuit for reducing power and maintainin proper current distribution during the avalanche erasure of a stored charge on floating gate memory elements in a large array of electrically alterable charge storage cells.

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Avalanche Erasure Current Control Circuit for EAROM Array

This article describes an FET circuit for reducing power and maintainin proper current distribution during the avalanche erasure of a stored charge on floating gate memory elements in a large array of electrically alterable charge storage cells.

Floating gate storage devices, such as the one shown in Fig. 1, have been proposed for the basic storage device or cell in an electrically alterable read-only memory (EAROM) array. The cell includes the P-type substrate 10 with N-type diffusions 12, 14 and 16. A floating gate 18 and a control or program gate 20 are embedded in an oxide layer 22. The N-type diffusion 16 is connected directly to a source V(E) of an erasure voltage. This diffusion 16 forms an N-P junction with the substrate 10.

To erase the device, the control gate 20 is grounded or taken negative while the voltage at V(E) is taken positive to avalanche the N-P junction. The negative control gate potential establishes an electrical field in a thin oxide region 24 separating N-type diffusion 16 and floating gate 18. When the N-P junction adjacent region 24 breaks down, avalanche current is injected into region 24. The field established across region 24 drives hot holes through the region to neutralize any electrons stored on floating gate 18.

The time required to neutralize the charge on the floating gate is proportional to the avalanche current at its erasure diffusion. Also, there is an upper limit to the maximum current that can be safely conducted through a junction in the avalanche condition. For large arrays of floating gate cells, it is not practical to selectively avalanche erasure diffusions in sequence in order to limit the current at each junction. Nor is it practical to avalanche all of the diffusions in parallel due to power dissipation and current hogging.

Therefore, the maximum current that can be conducted without destroying a single avalanching junction can be shared among a group of cells. The group size is...