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OP Code Extender

IP.com Disclosure Number: IPCOM000051444D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 4 page(s) / 91K

Publishing Venue

IBM

Related People

Balm, GJ: AUTHOR [+3]

Abstract

Computer systems normally allocate a predetermined number of bits to specify the operation code for instructions. For example, an eight-bit op code field has 256 op code points. When these are used up and expansion is desired, the op code field can be extended and in this instance is extended by placing a branch control word in the primary operation control table. The branch control word specifies a secondary operation control table, and entry into that table is specified by a four-bit extender field contained in the instruction. This arrangement does not require any new instruction formats, and makes use of instructions having previously unused instruction stream bits. Because of this, the new instructions can be handled by existing hardware and microcode using all of the instruction fetch hardware assists.

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OP Code Extender

Computer systems normally allocate a predetermined number of bits to specify the operation code for instructions. For example, an eight-bit op code field has 256 op code points. When these are used up and expansion is desired, the op code field can be extended and in this instance is extended by placing a branch control word in the primary operation control table. The branch control word specifies a secondary operation control table, and entry into that table is specified by a four-bit extender field contained in the instruction. This arrangement does not require any new instruction formats, and makes use of instructions having previously unused instruction stream bits. Because of this, the new instructions can be handled by existing hardware and microcode using all of the instruction fetch hardware assists. The unused field of certain previously defined instructions is a four-bit field, and thus allows extended op codes to be assigned in groups of 16.

The decode of the op code occurs at the end of each instruction processing cycle, and in this instance via a microcode control word. The op code bits 0-7 inclusive of the instruction 10 (Fig. 1) are a pointer into the primary operation control table 20. The microinstruction in the primary operation control table 20 initializes operation-dependent parameters and branches to applicable I-fetch paths 30, to op code routines 40 or to supervisory routine 50. Bits 8-15, which include the op code extender bits 12-15, are loaded in P and L registers 15 and 16, respectively. If a hardware-assisted implementation is used for the op code extension, a microcontrol word in the primary op code table 20 causes a branch to one of the secondary op code tables 60 (Fig. 2) where entry into the secondary op code table 60 is based upon bits 12-15 of the op code extension field in instruction 10. If a particular code point in the extended op code is not used, a branch instruction is placed at its entry point in the secondar...