Browse Prior Art Database

Quasi Synchronization of a Slow Speed Channel to a Direct Access Storage Device

IP.com Disclosure Number: IPCOM000051461D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Cheng, YP: AUTHOR [+4]

Abstract

Direct-access storage devices which employ an architecture for the reading and writing of data which requires that the host (attaching channel, main storage, etc.) be in precise synchronism with the rotating storage medium, also requires that data be transferred exactly at the rate of data reading or writing at the device. The data requests are made to the channel by the storage control providing the attachment of the device to the channel. These requests are made at the transfer rate of the device. The channel satisfies these requests on a demand-response basis at a rate necessary to keep up with the device transfer on the recording track.

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Quasi Synchronization of a Slow Speed Channel to a Direct Access Storage Device

Direct-access storage devices which employ an architecture for the reading and writing of data which requires that the host (attaching channel, main storage, etc.) be in precise synchronism with the rotating storage medium, also requires that data be transferred exactly at the rate of data reading or writing at the device. The data requests are made to the channel by the storage control providing the attachment of the device to the channel. These requests are made at the transfer rate of the device. The channel satisfies these requests on a demand-response basis at a rate necessary to keep up with the device transfer on the recording track.

If data is transferred at a rate less than that of the device, the storage device is said to "overrun" the data rate of the attaching channel and an exception condition exists which requires correction/retry action by the storage control, channel, or host (or some combination of the above). The Count-Key-Data (CKD) architecture employed in IBM disk files from the IBM 2311 through 3350 devices is a channel-device synchronous architecture, as described above. In particular, the definitions of channel programs and data formats are so intertwined that the channel programs of CKD architecture cannot be interpreted without a concurrent examination of data stored on the device.

When it is required to design the attachment of direct-access storage using channel-device synchronous architecture, such as described above, to a host (channel) with a maximum data transfer rate less than the data rate of the device, some mechanism must be added to the storage device or its control to accommodate the expected differences in transfer rates. A small speed matching buffer (implemented in electronic storage) may successfully provide such a mechanism for the reading of data; data from the storage medium accumulates in the buffer at the device transfer rate, while the channel removes data from the buffer at its slower rate. Such a buffer is less successful for the writing of data. Data...