Browse Prior Art Database

Double Port Register Chip Using Single Port Cells

IP.com Disclosure Number: IPCOM000051477D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Brantley, WC: AUTHOR [+2]

Abstract

In a two address vector instruction the destination register is both read and written for each element of the vector. If a vector processor is pipelined so that one element of the result is produced per cycle, then the destination register must be read and written in the same cycle. This article describes an arrangement which allows the register to be both read and written in the same cycle without requiring that the register be made up of double-port cells.

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Double Port Register Chip Using Single Port Cells

In a two address vector instruction the destination register is both read and written for each element of the vector. If a vector processor is pipelined so that one element of the result is produced per cycle, then the destination register must be read and written in the same cycle. This article describes an arrangement which allows the register to be both read and written in the same cycle without requiring that the register be made up of double-port cells.

The memory array configuration includes two memory arrays L and R, an address switch A, and a data out switch S. The memory arrays L and R are standard single-port arrays of flip-flops. That is, a memory array may be either read or written each cycle but not both. The two memories hold the even and odd vector elements, respectively. Thus, the even array L holds elements 0, 2, 4, ... , and the odd array R holds elements 1, 3, 5, ... .

In operation, elements are read sequentially and written sequentially but with a delay of D cycles. For example, if D=5, then element 6 would be read while element 1 was being written. This delay allows time for the information to be transformed in some way before being stored back in the array. D, the delay between reading and writing the same element, must be odd. Otherwise, if D were even, then one would attempt to read an element in the even array and also to write an element in the even array in the same cycle.

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