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Cache Line Reclamation and Cast Out Avoidance Under Operating System Control

IP.com Disclosure Number: IPCOM000051478D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Hoevel, LW: AUTHOR [+2]

Abstract

The number of line transfers between cache and processor memory, and th delay penalty for misses to uninitialized memory is reduced, as set forth below.

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Cache Line Reclamation and Cast Out Avoidance Under Operating System Control

The number of line transfers between cache and processor memory, and th delay penalty for misses to uninitialized memory is reduced, as set forth below.

The transitory nature of dynamically allocated storage can be exploited to reduce both the number of line transfers and the processor delay associated with certain misses. This requires special instructions that explicitly change the status of cache lines during GETMAIN-and FREEMAIN-like operations.

During allocation (GETMAIN), a "getline(s)" instruction would modify the cache directory to show the selected lines as "in-cache" without actually transferring the current contents of these lines from processor memory into the cache. It is permissible to do this because there is no presumption of integrity for the contents of newly allocated, as yet uninitialized storage. For security purposes, however, it may be necessary to clear the contents of such lines.

During de-allocation (FREEMAIN), a "freeline(s)" instruction would modify the cache directory to show that the selected line(s) are "unmodified" and "least recently used", denoting freed lines as unmodified (i.e., no stores performed to those lines). This obviates the need to write the lines back out to processor memory when they are eventually selected for replacement at a cache miss. Marking them as "least recently used" insures that they will be selected for replacement as soon as pos...