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Browse Prior Art Database

Concurrent Command Fetching For A Multiple Device I/O Controller

IP.com Disclosure Number: IPCOM000051503D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 5 page(s) / 100K

Publishing Venue

IBM

Related People

Brown, LW: AUTHOR [+3]

Abstract

A multiple-device input/output (I/O) controller is described whereby a device command may be fetched from a host processor main store and command set-up processing initiated for a second I/O device while a data transfer operation is underway with a first I/O device. The embodiment described herein is intended for use with an IBM Series/1 computer and, as such is constructed for attachment to the Series/1 I/O channel interface bus.

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Concurrent Command Fetching For A Multiple Device I/O Controller

A multiple-device input/output (I/O) controller is described whereby a device command may be fetched from a host processor main store and command set- up processing initiated for a second I/O device while a data transfer operation is underway with a first I/O device. The embodiment described herein is intended for use with an IBM Series/1 computer and, as such is constructed for attachment to the Series/1 I/O channel interface bus.

There is presently available a Series/1 I/O controller which is capable of servicing up to four I/O units or I/O devices.

Information transfer between the computer (host processor) main store and the controller can occur in one of two ways: microprocessor control and hardware control. The I/O controller fetches the user commands, analyzes the specified operation via microcode, and sets up the appropriate hardware to cause the specified transaction to occur.

If a large block of information is to be transferred between the host processor and an I/O device, the controller microprocessor sets up the controls and then invokes a hardware-controlled high speed data transfer. This method gives the user performance advantages for large data block transfers. However, when such a high speed transaction is underway, it is not possible to transfer, analyze, and set up a command for another I/O device.

The existing Series/1 four-device I/O controller is capable of transferring data in a cycle-steal mode to and from the Series/1 host processor under the direct control of the controller microprocessor or, alternatively, in a high-speed microprocessor bypass mode initiated by the microprocessor but controlled thereafter by the controller hardware and the I/O device hardware. These two methods of cycle stealing data cannot occur simultaneously. The microprocessor-controlled cycle-steal mode is generally used to gather command information at the beginning of an operation or to present cycle-steal status at the end of an operation. Although actual data can be transferred in this mode, the high speed data transfer mechanism is more suitable due to performance and is used for most data transfers. While the high speed data bypass is in operation transferring a block of data to or from the I/O device, the microprocessor, though not inactive, is prohibited from performing a cycle-steal transfer. Since the controller is a four-device controller, it is desirable not to prohibit the microprocessor from fetching Device Control Block (DCB) command information for one of the four devices while another device is transferring data in the high- speed bypass mode.

Fig. 1 is a block diagram of the portion of the existing Series/1 I/O controller that cycle steals data to and from the Series/1 host processor. The microprocessor (1) sets the Address Counter (2), the Byte Counter (3) and the Cycle-Steal (C/S) Address Key Register (6) to their starting values regardless of the mo...