Browse Prior Art Database

Maskless Solder Bump Interconnection Process

IP.com Disclosure Number: IPCOM000051529D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Gardiner, KM: AUTHOR [+2]

Abstract

This article describes a processing sequence for a large semiconductor wafer in which contacts are made to the semiconductor wafer by first depositing and personalizing a layer of photoresist and then depositing chrome, chrome copper, copper, tin and tin lead in a single vacuum system followed by a photoresist lift-off step. The semiconductor wafer is then joined to a solder ball previously deposited on a module substrate. This process eliminates the use of gold in an interconnection, and registration, alignment and differential thermal expansion of metal masks is avoided. The process steps include: 1. Deposit a uniform thick film of photoresist on a wafer after completion of processing to final via hole. 2. Expose and develop to remove photoresist in via and adjacent areas. 3.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

Maskless Solder Bump Interconnection Process

This article describes a processing sequence for a large semiconductor wafer in which contacts are made to the semiconductor wafer by first depositing and personalizing a layer of photoresist and then depositing chrome, chrome copper, copper, tin and tin lead in a single vacuum system followed by a photoresist lift-off step.

The semiconductor wafer is then joined to a solder ball previously deposited on a module substrate. This process eliminates the use of gold in an interconnection, and registration, alignment and differential thermal expansion of metal masks is avoided. The process steps include:
1. Deposit a uniform thick film of photoresist on a wafer after completion of processing to final via hole.
2. Expose and develop to remove photoresist in via and adjacent areas.
3. Cure photoresist as appropriate, and place in evaporator.
4. DC sputter clean, and evaporate chromium and copper to desired specifications.
5. Immediately evaporate a few microns of lead/ttn without breaking vacuum, preferably using a dual source with tin leading lead slightly to improve wettability to copper.
6. Strip the photoresist.
7. Use a normal reflow, test, dice sequence.
8. Build up the remainder of the solder volume required on the module substrate using either: a) a plating up directly technique, or

b) evaporation through metal masks, or

c) screening through metal masks.

1