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Delay Related Fault Detection Using Logic Test Data

IP.com Disclosure Number: IPCOM000051544D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 4 page(s) / 53K

Publishing Venue

IBM

Related People

Babiel, JJ: AUTHOR [+2]

Abstract

A test concept for detecting missing terminators and delay-related faults with logic test data is described. This approach does not require delay measuring between the start of signal stimulus and stop of the response. The fault detection is based on the presence or absence of a pulse.

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Delay Related Fault Detection Using Logic Test Data

A test concept for detecting missing terminators and delay-related faults with logic test data is described. This approach does not require delay measuring between the start of signal stimulus and stop of the response. The fault detection is based on the presence or absence of a pulse.

Terminators are resistors (and other passive devices) that minimize the signal reflections on a physical net. A missing terminator affects the delay on the net. In other words, a missing terminator affects the AC characteristics of the product.

DC non-logic resistance test can detect missing resistor terminators. The non-logic test is applied by turning off the power supply and doing a DC resistance measurement. There are test systems where it is not possible to do resistance tests on probable nets. The DC resistance test may only detect faults related to resistance. There are test systems where it is not possible to power down a device under test (DUT) to do a resistance test, and it is necessary to detect delay related faults. It is also important to provide a diagnostic technique to prioritize a module (or chips) to be replaced.

The described test concept can be implemented on a multi-chip-module (MCM) tester that uses a multi-pin probe to diagnose failures detected on the MCM. The approach can be tailored to a specific technology and tester, but the concept is applicable to other technologies. I. The Environment and Theory of the Implemented Version a) MCM Test Environment - This test concept can be used by the real-time "Probe" Diagnostic Algorithm to prioritize the chips to be replaced on the failing MCM. The MCM consisted of logic and terminator chips. The Probe Diagnostic Algorithm makes decisions that directed a multi-pin probe to as many probable chips as are required to diagnose a defect to a replaceable unit. This algorithm traces a failure from the primary output along a failing input net path. This trace continues until the dependent net's failing test occurs earlier that any of the input net's failing test. This failing dependent net is called the terminal net. The Probe Diagnostic Algorithm uses physical data that describes the physical nets and the subassemblies on the DUT. The physical net consists of the physical nodes and the interconnections between the nodes. The physical data contained all needed data (i.e., node characteristic-sink, source, terminator, node location) to position the probe on the DUT. The logic test data consists of a sequence of logic tests. The expected responses are referenced by the test number of the primary input stimulus. The expected responses consisted of logic states (1, 0, X) and glitch states (1 indicated that a glitch is expected, 0 indicated that a glitch is not expected, X is a "do not know" condition). A glitch was defined as any number of transition(s) within a single test. This test concept was tailored to the technology being tested. When t...