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Processing Intermixed Logic Structure

IP.com Disclosure Number: IPCOM000051545D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 4 page(s) / 80K

Publishing Venue

IBM

Related People

Zobniw, LM: AUTHOR

Abstract

This article describes a methodology and macro models which create test data for printed circuit boards (PCB) that have devices for which primitive logic (i.e., AND, OR, NOT) representation is available (PL devices) interfacing with VLSI (i.e., microprocessor and related functions) devices for which primitive logic representation is not available (PLNA devices). This methodology uses automatic test generation (ATG) with fault simulation to create tests for the PCB portions consisting of PL devices and uses behavioral simulation (BSIM) to create functional speed test data for the entire PCB (PL devices interfacing with PLNA devices). During ATG, this methodology requires that the PL devices be electrically isolated from the PLNA devices.

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Processing Intermixed Logic Structure

This article describes a methodology and macro models which create test data for printed circuit boards (PCB) that have devices for which primitive logic
(i.e., AND, OR, NOT) representation is available (PL devices) interfacing with VLSI (i.e., microprocessor and related functions) devices for which primitive logic representation is not available (PLNA devices). This methodology uses automatic test generation (ATG) with fault simulation to create tests for the PCB portions consisting of PL devices and uses behavioral simulation (BSIM) to create functional speed test data for the entire PCB (PL devices interfacing with PLNA devices). During ATG, this methodology requires that the PL devices be electrically isolated from the PLNA devices. During BBIM, PLNA devices are represented with behaviors, and designer-supplied stimuli are applied against the BSIM structure (consisting of behaviors and primitive logic) to create the PCB responses. Behavior is a high level functional description of a device or function. A behavior is similar to a PL/I program invoked by the BSIM simulator to propagate a logic value from primary inputs to primary outputs.

Since ATG requires that PCB structure be represented with primitive logic, this methodology replaces PLNA devices with general-purpose (GP) non- controlling (NONC) and XOUT macros (Figs. 1 and 2). These macros are general purpose because they can represent a "black-box" block with any number of pins. During ATG, the GP primitive logic is inhibited to allow ATG to generate tests for the PL devices.

The XOUT macro shown in Fig. 1 creates an "X" (unknown) state at all macro outputs (no matter what the stimuli). The NONC macro (Fig. 2) provides control line(s) that can place the macro's outputs at a non-controlling state or at "X" state. (Note: Tri-state devices and microprocessor devices have such control lines.) During ATG, the control lines are used to inhibit (place in non-controlling state) the PLNA device outputs. The NONC and XOUT logic is not faulted; therefore, ATG will not attempt to create tests for the NONC and XOUT. XOUT is used when PLNA device outputs go directly to primary output or PLNA device outputs go to an isolating circuit (i.e., tri-state driver). NONC is primary output from PLN...