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Integrated Checking for High Speed Array Multiplier

IP.com Disclosure Number: IPCOM000051557D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Carter, EL: AUTHOR [+2]

Abstract

A known high-speed array multiplier is modified with minimal additiona hardware and without redundant hardware to provide checking of the array.

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Integrated Checking for High Speed Array Multiplier

A known high-speed array multiplier is modified with minimal additiona hardware and without redundant hardware to provide checking of the array.

The basic multiplier hardware consists of level sensitive scan design (LSSD) input registers 10, 11, output register 12 and array multiplier 13. Array 13 allows multiplication to be done in a high-speed, parallel operation. In the processor system in which they are found, registers 10-12 are used for testing/diagnostic purposes and for system compatibility. Each of the LSSD registers 10-12 is configured as a scan string shift register, with each latch of the shift register being utilized in the scan string. The LSSD data (LSSD SCAN IN, LSSD SCAN OUT) can be shifted into or out of the particular register 10-12 independent of the arithmetic system data at inputs X and Y. In normal operational mode, the multiplier system operates in its SYSTEM DATA mode in response to the DATA SELECT logic 14, 15 which is activated to accept the SYSTEM DATA input 10A, 11A.

In the checking mode, the DATA SELECT logic 14, 15 is activated to respond to the SCAN DATA inputs 10B, 11B. Using the existing LSSD hardware 10-12 and array multiplier 13, the checking function is accomplished as follows: Fixed,
i.e., known, words (X and Y) are loaded into input registers 10 and 11 via the LSSD scan string, and the corresponding expected product output word (X x Y) is loaded into output register 12. +Th...