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Digital Phase Locked Tone Detector

IP.com Disclosure Number: IPCOM000051559D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Crow, RF: AUTHOR

Abstract

A phase-locked circuit discriminates against input signals A not havin a desired input frequency f, which, for purposes of explanation, is assumed to be one KHz.

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Digital Phase Locked Tone Detector

A phase-locked circuit discriminates against input signals A not havin a desired input frequency f, which, for purposes of explanation, is assumed to be one KHz.

Input signal A is fed to the common input of phase-locked cicuit 10 and inverter 14. In response to the falling edge of signal A, single-shot multivibrator 11 provides an output pulse B of short duration t, e.g., t = 1 mu sec., for each input cycle. Pulse signal B resets digital counter 12 which, in response to a clock signal at its input CLOCK, provides a square wave output signal C at the desired output frequency. For this purpose and example, counter 12, in response to a crystal oscillator input signal of 1 MHz at its input CLOCK, provides a divide-by-1000 function, resulting in an output signal of 1 KHz. The output signal C is exclusively ORed by exclusive OR gate 13 with the inverted signal D of the input signal A provided by inverter 14. The output signal E of gate 13 is integrated by RC integrator 15, 16, and its resultant output signal F is compared with a reference voltage Vref in comparator 17. Circuits 13, 15-17 are configured as a detector 18.

As shown by the waveform set I, when the input signal A is at the correct frequency f, signals A and C are phase-locked, resulting in signals C and D being complementary. Thus, the output signal G (wave-form set I) of comparator 17 is at its up level. If the input signal A is at a lower frequency, the output signal G i...