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Browse Prior Art Database

Cache Reconfiguration

IP.com Disclosure Number: IPCOM000051560D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Hrustich, J: AUTHOR [+2]

Abstract

In a storage controller that utilizes a high speed cache to increase performance, it is possible to increase the cache size without adding much additional cost. It is also possible to make the data page size variable and to provide a back-up cache in the event of a failure. This applies to many applications, such as reconfiguration, when an error occurs, maintaining additional code, duplication checking, etc.

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Cache Reconfiguration

In a storage controller that utilizes a high speed cache to increase performance, it is possible to increase the cache size without adding much additional cost. It is also possible to make the data page size variable and to provide a back-up cache in the event of a failure. This applies to many applications, such as reconfiguration, when an error occurs, maintaining additional code, duplication checking, etc.

This description illustrates how a 16K-byte cache would be implemented using 1K by 9 arrays. Using the same 1K X 9 arrays, other sizes could be implemented to increase cache size to 48K or 64K, but this configuration best illustrates the design.

The data flow width is 8 bytes and the cache page size can be 64, 128, 192 or 256 bytes, i.e., (8X8), (8X16), (8X24) or (8X32). There are also 8 slots of associativity within the cache, as shown in the drawing.

When in a 16K-byte-mode cache, address lines A0 through A7 will address the cache and lines A8, A9 are held in a steady state. If a failure is detected in this 16K-byte region, A8 and/or A9 can be altered in an attempt to bypass the failure, thus resuming system operation.

When in a 32K-byte-mode cache, address lines A0 through A8 will address the cache and A9 is held in a steady state. If a failure is detected in this 32K byte, A9 can be altered in an attempt to bypass the failure.

Latches 3, 5, which are set/reset by the Instruction Processor Unit (IPU) and are connected to A8 and A9 in...