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Address Mapped Input/Output Interface

IP.com Disclosure Number: IPCOM000051561D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Oliver, BL: AUTHOR

Abstract

This description relates to a method to interface Universal Controller (UC) architected adapters to a general-purpose 16-bit processor. Because of the availability of inexpensive 16-bit processors, it is desirable to be able to attach existing devices by matching the UC/IO interface. Emphasis is on performing an IO (input/output) operation in one processor instruction cycle.

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Address Mapped Input/Output Interface

This description relates to a method to interface Universal Controller (UC) architected adapters to a general-purpose 16-bit processor. Because of the availability of inexpensive 16-bit processors, it is desirable to be able to attach existing devices by matching the UC/IO interface. Emphasis is on performing an IO (input/output) operation in one processor instruction cycle.

UC adapters are designed to operate in two modes: PIO (Programmed IO) and cycle steal. PIO operations occur as a result of the execution of an IO instruction. These instructions are of an immediate nature, that is, a unit of data is transferred either to or from an adapter within the execution time of the instruction.

UC adapters can be either a byte or halfword in width; therefore, the unit of data can be a byte or halfword. In addition to the unit of data, two other bytes are required by the adapter to perform the PIO instruction. First, a byte of information is required to identify the appropriate adapter, the address byte. Secondly, a byte of information is required to identify the command that the adapter is to perform.

UC architecture describes the PIO operation as a three sequence procedure. These sequences occur at the following times: TA, TC, and TD, where TA is address time, TC is command time, and TD is data time. Since halfword adapters are implemented with 2-byte busses, TA and TC may occur at simultaneous times. For byte adapters, these times are always sequential.

The following summarizes the adapter requirements to perform an IO operation.
1) TA time - a byte of information must be sent to

the adapter defining adapter address.
2) TC time - a byte of information sent to the adapter

defining the adapter command.
3) TD time - either one or two bytes of data sent to

or received from the adapter.

The following description explains a means of obtaining four bytes of information from a processor with two-byte data flow. Since information is sent to the adapter during both TA and TC, regardless of whether the adapter is performing a read or write operation, these bytes can be obt...