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Partial Parity Predict for CPU having Architectural Rotate and Mask/Merge Unit

IP.com Disclosure Number: IPCOM000051563D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Schaughency, MF: AUTHOR

Abstract

Certain computer architectures include instructions which utilize or need a rotate and mask/merge unit. This CPU unit takes an operand, rotates it a specified amount (0 to 32 bit) positions (bits shifted out being shifted in the opposite end), and then, under control of a mask of ones and zeros, gates out bits of the rotated word where the mask is ones, and gates out bits of a second operand (forced zeros for some instructions) where the mask is zeros. The possible combinations of shift amount, mask configuration, and data inputs could be very large, which initially discouraged any attempt to detect picked up or dropped data bits.

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Partial Parity Predict for CPU having Architectural Rotate and Mask/Merge Unit

Certain computer architectures include instructions which utilize or need a rotate and mask/merge unit. This CPU unit takes an operand, rotates it a specified amount (0 to 32 bit) positions (bits shifted out being shifted in the opposite end), and then, under control of a mask of ones and zeros, gates out bits of the rotated word where the mask is ones, and gates out bits of a second operand (forced zeros for some instructions) where the mask is zeros. The possible combinations of shift amount, mask configuration, and data inputs could be very large, which initially discouraged any attempt to detect picked up or dropped data bits.

However, the mask has a limited number of configurations. It is either a string of ones surrounded by (zero or more) zeros, or a string of zeros surrounded by (zero or more) ones. This means that with a 32-bit operand, for example, at least two bytes will have an all-zeros and/or an all-ones mask. Therefore, parity for these bytes may be gated through from the appropriate source.

A substantial portion of real-world instructions will have an all-ones mask. This means that parity would be unchanged for the whole 32-bit word regardless of parity change on each byte due to shift amounts from byte boundaries and/or will have a shift amount of 0, 8, 16, or 24 positions, which means that byte parity may be simply shifted with the data. Also, a substantial portion of real-world instructions will have masks aligned on byte boundaries. In thes...