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Method of Contacting Shallow Emitters

IP.com Disclosure Number: IPCOM000051569D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Barson, F: AUTHOR

Abstract

Metallizing very shallow emitters of bipolar transistors has proven difficult, since device degradation occurs when platinum (Pt) is sintered to form the PtSi ohmic contacts. This is believed to be due to excessive penetration by the PtSi formed especially at the emitter perimeter where the lateral diffusion is less than the vertical junction depth. Also, there is an extended layer of Pt over the adjacent insulator during sintering so that greater penetration occurs at the emitter edge in order to satisfy the solubility of the additional overlying Pt within a diffusion length or two.

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Method of Contacting Shallow Emitters

Metallizing very shallow emitters of bipolar transistors has proven difficult, since device degradation occurs when platinum (Pt) is sintered to form the PtSi ohmic contacts. This is believed to be due to excessive penetration by the PtSi formed especially at the emitter perimeter where the lateral diffusion is less than the vertical junction depth. Also, there is an extended layer of Pt over the adjacent insulator during sintering so that greater penetration occurs at the emitter edge in order to satisfy the solubility of the additional overlying Pt within a diffusion length or two.

A method to minimize these effects by providing an increased separation laterally between the contact area and the emitter junction and thus minimizing device degradation is given as follows:

a) A layer 10 approximately 500 Angstroms-1000 Angstroms of chemical vapor deposited (CVD) SiO(2) is deposited onto the wafer surface just prior to the poi at which Pt is normally deposited, that is, when the emitter 12 has been formed and contact holes are open in the masking layer consisting of, for example, SiO(2) layer 14 and Si(3)N(4) layer 16, as shown in Fig. 1.

b) Directional reactive ion etching is used to remove the CVD film, leaving most of the film 10 at the perimeter and stopping at the Si interface, as shown in Fig. 2. The contact hole has now been narrowed on each edge by about the thickness of deposited CVD SiO(2) layer 10.

c) The Pt is then...