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Improved NPN Process and Structure

IP.com Disclosure Number: IPCOM000051585D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Barson, F: AUTHOR

Abstract

A self-aligned NPN transistor with an oxide insulator bounding the extrinsic base layer is shown in Fig 1. The key steps (not shown) in forming the SiO(2) layer between the P/+/ polysilicon and the underlying subcollector (N/+/) involve etching the epi layer down to the subcollector prior to forming the base and emitter regions, and oxidizing thermally at low temperature. This produces a much thicker SiO(2) film on the N/+/ subcollector as compared to the N /-/epi exposed on the sidewall of the etched depression. A dip etch can then be used to completely remove the oxide on the N/-/ sidewall while leaving an SiO(2) film over the subcollector region. Subsequent polysilicon deposition to fill the depression, etc., results finally in the structure of Fig. 1.

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Improved NPN Process and Structure

A self-aligned NPN transistor with an oxide insulator bounding the extrinsic base layer is shown in Fig 1. The key steps (not shown) in forming the SiO(2) layer between the P/+/ polysilicon and the underlying subcollector (N/+/) involve etching the epi layer down to the subcollector prior to forming the base and emitter regions, and oxidizing thermally at low temperature. This produces a much thicker SiO(2) film on the N/+/ subcollector as compared to the N /-/epi exposed on the sidewall of the etched depression. A dip etch can then be used to completely remove the oxide on the N/-/ sidewall while leaving an SiO(2) film over the subcollector region. Subsequent polysilicon deposition to fill the depression, etc., results finally in the structure of Fig. 1.

A modification is disclosed for improvement by eliminating the shallow oxide isolation separating the N/+/ reach-through (the collector contact) from the P/+/ polysilicon base contact. (The oxide region eliminated is indicated as "shallow isolation" in Fig. 1.) This is done by simply omitting the formation of that oxide region from the process and permitting the etched depression, which is later to be filled with P/+/ polysilicon, to overlap the N/+/ reach-through region. The low temperature thermal oxidation used to form thick SiO(2) on the underlying subcollector will then also grow a thick SiO(2) on the N/+/ sidewall at the reach- through, but still a thin SiO(2) film on the...