Browse Prior Art Database

Inverted Input Push Pull Driver

IP.com Disclosure Number: IPCOM000051587D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Gaudenzi, GJ: AUTHOR [+2]

Abstract

The driver circuit shown is a push-pull-type driver (which may be implemented as an open collector) capable of driving loaded transmission lines (high capacitance) while limiting the output down-going dv/dt to acceptable values via the inverted mode of operation of transistor T1.

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Inverted Input Push Pull Driver

The driver circuit shown is a push-pull-type driver (which may be implemented as an open collector) capable of driving loaded transmission lines (high capacitance) while limiting the output down-going dv/dt to acceptable values via the inverted mode of operation of transistor T1.

When T1 is operated in the inverted mode (as compared to prior-art forward mode operation), the rate of change of base current and, therefore, collector current of transistor T3 is slowed down which, in turn, reduces the rate at which the output voltage falls (dv/dt). Falling dv/dt magnitudes of 450 mV/ns are achievable with considerable savings in silicon area realized over the prior-art feedback capacitor approach to limiting dv/dt. The inverted-mode approach also has the advantage of AC assurance of dv/dt via DC final test.

The nominal output rise delay of the circuit is 5.4 ns, and the nominal output fall delay is 2.5 ns for a load capacitance of 20 pf. Another advantage of the configuration is that due to the quiet state of transistor TD2 during output switching down, transient current flow in VCC is eliminated, which reduces power supply noise.

Diodes S1A and S1B are included to prevent high transient current flow in TD2 when output is driving long unterminated transmission lines and output drops below ground (approximately -1 V).

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