Browse Prior Art Database

Low End Memory Interface Driver Circuit

IP.com Disclosure Number: IPCOM000051588D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Gaudenzi, GJ: AUTHOR [+4]

Abstract

This interface circuit accepts input logic signal levels of 1.0V to 1. and provides output logic signal levels of 0.2V to O.SV at 220 microamperes (down-level) and 2.7V to 3.4V at 220 microamperes (up-level), while performing the INVERT logic function.

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Low End Memory Interface Driver Circuit

This interface circuit accepts input logic signal levels of 1.0V to 1. and provides output logic signal levels of 0.2V to O.SV at 220 microamperes (down- level) and 2.7V to 3.4V at 220 microamperes (up-level), while performing the INVERT logic function.

The 2.7V minimum up-level enables the circuit to drive FET memory products requiring up-levels in excess of 2.7V in order to insure adequate noise margin.

An up-level at the input turns on T1 and T4, holding the output at a down- level. D3 sets the threshold for turning on T1. The base of T2 is pulled down through R1 enough to keep its emitter below 0.5V. The value of R3 is chosen so as to suppress down-level external network ringing and to limit the down-level conduction of T2 to a low value. This marginal conduction of T2 aids in up-going performance when the input is brought to a down-level.

When the input is brought down, T1 and T4 are held off. D3 and R4 discharge the base of T4. The collector of T1 rises through R1, turning T2 on and pulling the output to an up-level. This occurs until T3 turns on enough to begin to turn T2 off, at which point the up-level is clamped. The potential at which clamping occurs is accurately set by the ratio of R1 and R2. T3 is prevented from saturating because T2 holds the collector of T3 one VBE potential above its base. D1 and D2 prevent T1 and T4 from saturating.

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