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Clocked Phase Splitter

IP.com Disclosure Number: IPCOM000051596D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Heimeier, HH: AUTHOR [+4]

Abstract

In a monolithic integrated phase splitter circuit one of the two hithe necessary clock lines which require a relatively high amount of space, because they must be of a very low impedance, are replaced by a transistor and a simple control line.

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Clocked Phase Splitter

In a monolithic integrated phase splitter circuit one of the two hithe necessary clock lines which require a relatively high amount of space, because they must be of a very low impedance, are replaced by a transistor and a simple control line.

Fig. 1 shows a conventional phase splitter circuit with input 1 and the two outputs 0 and 0 for the signals of opposite phase. This type of phase splitter is used if the circuit has to be completely turned off, for instance, during the standby phase of an array, to decrease power dissipation. The circuit requires two broad clock lines CL1 and CL2 whose potential is to be lowered successively (see the timing diagram of = Fig. 2). If only one clock line were used, the consequence would be that when transistor T1 is conductive, transistor T2 would for a short period be conductive, too, until transistor T3 has become equally conductive following Tl, and has taken over the base current from T2. This would cause at output 0 an undesired negative voltage drop (glitch). This is prevented by providing for T2 its own clock line CL2 whose potential is lowered after that of clock line CL1.

In the circuit of Fig. 3, one of the two clock lines required for the circuit of Fig. 1 is replaced by transistor T4 and control line C with resistor R4. Prior to the lowering of the potential of the clock line, control line C shows the up level (see the timing diagram of Fig. 4). T4 is thus conductive and the base-emitter junc...