Browse Prior Art Database

Bootstrap Driver Stage

IP.com Disclosure Number: IPCOM000051597D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Arzubi, L: AUTHOR [+4]

Abstract

As an application example of an improved bootstrap configuration with switchable bootstrap loop, a driver is proposed in which the bootstrap capacitor is not charged from the input but by the power supply voltage VH. When this driver is switched off, the bootstrap capacitor is discharged only to VH, thus considerably reducing the power dissipation and relieving the input driver.

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Bootstrap Driver Stage

As an application example of an improved bootstrap configuration with switchable bootstrap loop, a driver is proposed in which the bootstrap capacitor is not charged from the input but by the power supply voltage VH. When this driver is switched off, the bootstrap capacitor is discharged only to VH, thus considerably reducing the power dissipation and relieving the input driver.

In the largely conventional driver circuit, as shown, bootstrap capacitor CB is charged, via transistor 1, from supply voltage VH to only VH - 2 VT in the first driver cycle, since the potential at node E is as little as VH - VT (VT being the threshold voltage). The delay time of the driver until the charging of load capacitor CL begins is determined by the delay capacitor :CD at node A, which is charged in the restore phase (pulse R), and by its discharge path via transistors 8 and 9.

At the end of the delay time (node A has been discharged via transistors 8 and 9), FETs 3, 5, and 7 are switched off. Simultaneously, transistors 4 and 2 are switched on, as the current from transistor 6 no longer flows to ground via transistor 7 but to node C at the gates of transistors 2 and 4. In the subsequent bootstrap operation the gate of transistor 6 is raised to ~1.8 VH via CA, thus connecting the gates of transistors 2 and 4 to CB. The subsequently conductive transistor 4 charges node C to about 1.5 VH via CB and transistor 6, so that load capacitance CL can be charged to VH via transistor 2. To permit raising node B to 1.5 VH, the voltage at the gate of transistor 1 (node E) must not exceed VH VT at that time. This is achieved by connecting node D to ground via transisto...