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Process Independent Delay Driver

IP.com Disclosure Number: IPCOM000051598D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Kilmer, C: AUTHOR

Abstract

In an FET delay driver circuit the ratio of the differing delay times under worst-case and best-case performance, due to process parameter variations in production, is reduced.

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Process Independent Delay Driver

In an FET delay driver circuit the ratio of the differing delay times under worst-case and best-case performance, due to process parameter variations in production, is reduced.

Fig. 1 shows a standard bootstrap driver which, after the arrival of an input pulse b, emits a delayed output pulse bd. Fig. 2 shows the associated timing diagram.

Prior to the arrival of pulse b, pulse a ensures that the output terminal BD is discharged via FET 3, and C is discharged via FETs 4 and 5; node D is pre-charged, via FET 6, and node E via FET 7 to voltage VH-VT. Upon its arrival, pulse b proceeds via FET 8 to the gate of FET 1, which is turned on. Pulse b also reaches the gate of FET 9, which is activated and starts discharging node D.

Only when FET 2 is non-conductive after the discharge of node D does the potential at output BD rise, because the output terminal is now charged by FET 1.

Compared with the circuit of Fig. 1, the circuit of Fig. 3 additionally comprises FETs 12, 13 and 14. The function of T12 is to recharge slightly the gate of FET 2 which is discharged by FET 9.

The delay time for output pulse bd is thereby slightly extended.

In the circuit of Fig. 3, the bootstrap effect through which (by means of capacitor C2) the gate potential of FET 1 is raised via V(H) starts slightly earlier, as the gate capacity of FET 2 does not directly effect node D as in the circuit of Fig. 1. Proper bootstrapping is guaranteed by a feedback connectio...