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# Circuit for Multilevel Logic Implementation

IP.com Disclosure Number: IPCOM000051610D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 40K

IBM

## Related People

Beilstein, KE: AUTHOR [+2]

## Abstract

A multilevel logic circuit is disclosed employing FET devices having dissimilar active device threshold voltages.

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Circuit for Multilevel Logic Implementation

A multilevel logic circuit is disclosed employing FET devices having dissimilar active device threshold voltages.

Fig. 1 shows the improved multilevel logic inverter, and Fig. 2 illustrates its input and output voltage characteristics.

The circuit is a basic 4 voltage level inverter which operates as follows: For illustration purposes, quaternary logic for n-channel FET depletion-mode load technology is employed, as is described in U.S. Patent 4,202,044. However, the concept disclosed may be extended to any level of logic within practical limitations. Assume that the quaternary logic levels of "0," "1," "2" and "3" correspond to voltage levels of 0V, 3V, 6V and 9V, respectively. The circuit of Fig. 1 has active FET device threshold voltages (V(T)) of 7.5 volts for Q(1) and Q(3), 4.5 volts for Q(2), Q(4) and Q(7), and 1 volt for Q(5) and Q(6).

When the input signal voltage V(in) = 0V, devices Q(1) through Q(5) are OFF and devices Q(6) and Q87) are ON. None of the active device branches A(1) through A(3) is conductive, resulting in V(out) = 9V.

When V(in) = 3V, devices Q(1) through Q(4) are OFF, Q(6) and Q(7) are ON. Thus branch A(2) is conducting, and V(out) = 6V.

When V(in) = 6V, devices Q(2), Q(4) and Q(5) are ON, and device Q(6) is OFF, branch A(1) is conducting, and V(out) = 3V.

With V(in) = 9V, devices Q(1) through Q(5) are ON and devices Q(6) and Q(7) are OFF. Thus only branch A(3) conducts, resulting in V(out) = 0...