Browse Prior Art Database

Post Suspend Resume

IP.com Disclosure Number: IPCOM000051620D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 15K

Publishing Venue

IBM

Related People

Calta, SA: AUTHOR [+3]

Abstract

This article describes an I/O channel command and data processor instruction which permit programs running on central processors of a data processing system to influence the suspension and continuation of I/O channel operations, and provide programs with access to channel status information without invocation of system interruptions and associated programming overhead. A POST/SUSPEND channel command word (CCW), as defined herein, and a RESUME I/O instruction, also defined herein, respectively provide these suspension and continuation functions.

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Post Suspend Resume

This article describes an I/O channel command and data processor instruction which permit programs running on central processors of a data processing system to influence the suspension and continuation of I/O channel operations, and provide programs with access to channel status information without invocation of system interruptions and associated programming overhead. A POST/SUSPEND channel command word (CCW), as defined herein, and a RESUME I/O instruction, also defined herein, respectively provide these suspension and continuation functions.

The POSI/SUSPEND CCW requires the channel in which it is being executed to post status information in an area of system main storage which is located indirectly by address information in the command. It also conditions the channel to suspend operation relative to a device if a command chaining bit in the CCW is off and a suspend bit in the initial channel address word (CAW) is on. It also requires the channel to include a bit in the posted status information indicating whether it has or has not taken a suspension action.

The RESUME instruction is an I/O instruction designed for central processor execution. It instructs the executing processor to initiate continuance of command chained I/O operations in a channel which normally is in a suspended condition when the instruction is executed. The executing processor does not have to communicate a CAW to the designated channel inasmuch as that channel will have preserved the address of the command in process when it took the suspension action. The channel begins the resumed operation with the CCW which it would have fetched next had it not taken the suspension action and had it been instructed by its last CCW to chain to another CCW.

The POST/SUSPEND CCW is a 64-bit expression having the following form:
Bits 0-7: define the Operation Code
Bits 8-31: define the address in main storage of a pointer parameter, which in turn defines an address location

at which the channel is to post data

Bits 32-36: represent flag bits including a command chaining flag bit (bit 33)

Bits 37-47: not used Bit 48: zero

Bits 49-63: represent data--e.g., a status field--to be posted at the address defined by the pointer

parameter located by means of bits 8-31.

The data in bits 48-63 is stored in the memory space defined by the pointer located by means of bits 8-31. Thereafter, the value of that pointer is increased by 2 so that it points to a next posting position two bytes removed from the position currently being addressed. This next position is accessible for posting status of another subchannel or channel. If the command chaining flag bit (bit
33) is off, and if the "suspend flag" bit is on in the initial channel address word (CAW) which defines the location of the initial command in the chain associated with the present CCW, the channel suspends operation in respect to the sub-

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channel and device which it is currently servicing. The de...