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Two or More Detector Circuit

IP.com Disclosure Number: IPCOM000051641D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Goldstein, AD: AUTHOR

Abstract

The problem of detecting two or more logic lines simultaneously enable at once is common. One such problem is bus contention, where two external devices are in contention for the same bus line. The classic means of sensing this condition requires an excessive number of gates. The circuit described here uses far less logic, and still solves this problem in the digital domain. For example, if 64 enable lines are to be monitored, 64! over (2!) (62!) or 2016 gates would be required. This two or more detector circuit would require only 28 chips.

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Two or More Detector Circuit

The problem of detecting two or more logic lines simultaneously enable at once is common. One such problem is bus contention, where two external devices are in contention for the same bus line. The classic means of sensing this condition requires an excessive number of gates. The circuit described here uses far less logic, and still solves this problem in the digital domain. For example, if 64 enable lines are to be monitored, 64! over (2!) (62!) or 2016 gates would be required. This two or more detector circuit would require only 28 chips.

The basic functional block 10 consists of eight data inputs (a through h), an error line (E), and an output carry line (C). An enable input line (EI) is also provided for gating on and off the data input lines. When active low, the input lines a through h are checked for an error condition. Whenever any two or more input lines are enabled (active low), the Error output goes low. If one or more inputs are enabled, the Carry C output goes low. The carry feature can be used for cascading functional blocks together, as in Fig. 2. When cascaded, the occurrence of two or more carry output enabled at once must also be detected and flagged as an error. This accounts for the use of the ninth functional block in Fig. 2.

The heart of functional block 10, shown in Fig. 3, consists of two 8 line to 3 line priority encoders 12 and 13. The two encoders are connected in such a way that the input priorities are the...