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Reversible Sensing Logic

IP.com Disclosure Number: IPCOM000051644D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Calva, JR: AUTHOR [+2]

Abstract

The communications adapter (CA) described in the IBM Technical Disclosure Bulletin 23, 2461-2463 (November 1980) requires circuity for generating interrupt requests, i.e., a service function and circuitry for monitoring modem signals, such as Data Set Ready, Clear to Send and Receive Line Signal Detect. The reversible sensing logic accomplishes the sensing and latching of a logic 1 condition (the service function) or the sensing and latching of a logic B condition (the monitor function). The number of circuits required are much less than would be required when monitoring for a change of state using a flip-flop, exclusive-OR logic, and interrupt request logic circuits.

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Reversible Sensing Logic

The communications adapter (CA) described in the IBM Technical Disclosure Bulletin 23, 2461-2463 (November 1980) requires circuity for generating interrupt requests, i.e., a service function and circuitry for monitoring modem signals, such as Data Set Ready, Clear to Send and Receive Line Signal Detect. The reversible sensing logic accomplishes the sensing and latching of a logic 1 condition (the service function) or the sensing and latching of a logic B condition (the monitor function). The number of circuits required are much less than would be required when monitoring for a change of state using a flip-flop, exclusive-OR logic, and interrupt request logic circuits.

For a service function, a logic 1 level is latched until the condition requiring service, such as an interrupt, is satisfied.

Latch 120 (Fig. 1) is one bit of the status register described in the above referenced publication which is used to indicate a requirement for service. The condition and condition clock are applied to AND circuit 111 to set latch 120 via OR circuit 113. Latch 120 remains set until reset by a signal from AND circuit 141 via OR circuit 118.

Also, for the service function, terminal 130 receives a logic 0 level. This has the effect of eliminating inverter 140 and AND circuit 141 which are required only for the monitor function.

The monitor function requires the logic of Fig. 2 which includes AND circuit 142 for passing a COND CLK signal in response to receiving a T2 timing signal, an IOR (I/O READ) signal, and ABO (Addres...