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Browse Prior Art Database

Address Mark Recognition Circuit

IP.com Disclosure Number: IPCOM000051645D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 5 page(s) / 122K

Publishing Venue

IBM

Related People

Friesen, JH: AUTHOR

Abstract

The address mark recognition circuit constitutes an improvement on [*] and in particular allows the file data synchronizing circuit of [*] to correctly synchronize on address marks without being influenced by the variable frequency oscillator 42 erroneously getting into synchronism. The recognition circuit is particularly concerned with the magnetic sector 100, shown in Fig. 2, which includes the following fields: gap 1, VFO sync, AM (address mark), ID, CRC, gap 2, data sync field, AM (address mark) and data. The field 100 is located on magnetic disk 102, shown in Fig. 1. Fig. 3 duplicates most of the circuitry of [*] but with the lines 112, 46, 44, 107, 68, 105 and 114 being brought out and with the counter 56 of [*] being replaced by the bit-latch circuitry 56A, and Fig.

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Address Mark Recognition Circuit

The address mark recognition circuit constitutes an improvement on [*] and in particular allows the file data synchronizing circuit of [*] to correctly synchronize on address marks without being influenced by the variable frequency oscillator 42 erroneously getting into synchronism. The recognition circuit is particularly concerned with the magnetic sector 100, shown in Fig. 2, which includes the following fields: gap 1, VFO sync, AM (address mark), ID, CRC, gap 2, data sync field, AM (address mark) and data. The field 100 is located on magnetic disk 102, shown in Fig. 1. Fig. 3 duplicates most of the circuitry of [*] but with the lines 112, 46, 44, 107, 68, 105 and 114 being brought out and with the counter 56 of [*] being replaced by the bit-latch circuitry 56A, and Fig. 4 in particular shows the address mark recognition circuit connected electrically with the Fig. 3 circuitry.

The synchronizing circuit of [*] starts counting bytes of a data string from the first data bit detected after variable frequency oscillator 42 is in synchronism. If oscillator 42 synchronizes incorrectly (such as if an all-zeroes pattern is magnetically written in gaps 1 and 2), the first data bit on which the synchronizing circuit of [*] starts counting down is not the first data bit of the address mark, as it should be. The address mark recognition circuit described here will actually read the data and clock bit strings output from the variable frequency oscillator 42 and allow the circuitry to start counting down to the user specified byte only when a true address mark is found.

The recognition circuit shown in Fig. 3 includes a showing of the bit-latch circuitry 56A having the -VFO Sync line 105 and the +First Data Bit line 68 as inputs and having the +Count Byte line 58 as an output, the lines 105, 68 and 58 being shown in Fig. 3. In addition, the bit-latch circuitry 56A includes the -AM Found line 120 and the -AM Read line 122 as inputs. The bit-latch circuitry 56A, as shown in Fig. 4, includes the bit counter 56a which is the same as the bit counter 56 in the publication but modified, and an AM Read latch and Count Byte gate circuit 124. The END Byte line 126 and the END AM line 128 output bit counter 56a to circuit 124, and circuit 124 has the +Count Byte line 58 shown in Fig. 3 and in [*] as its output.

The recognition circuit shown in Fig. 4 includes 16-bit shift register 130 connected in parallel with 16-bit comparator 132, which in turn is connected in parallel with compare logic 134. Input lines 46, 107 and 44 are provided for register 130, and input lines 112 and 114 are provided for compare logic 134. Comparator 132 has an output 136 connected with control record logic 138, which in turn is connected with panel light 140. Comparator 132 also has line 142 carrying the +Byte Found signal as an output which is connected to the AM read bit counter 144. AM read bit counter 144 also has line 107 as an input and h...