Browse Prior Art Database

High Performance Implementation of MTL

IP.com Disclosure Number: IPCOM000051688D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 77K

Publishing Venue

IBM

Related People

Feth, GC: AUTHOR [+2]

Abstract

This article relates to merged transistor logic (MTL) circuits, and mo particularly, it relates to modification of such circuits which make them more amenable to high speed applications.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

High Performance Implementation of MTL

This article relates to merged transistor logic (MTL) circuits, and mo particularly, it relates to modification of such circuits which make them more amenable to high speed applications.

Extension of MTL to higher speed logic applications has been inhibited by several factors. Switching is retarded by charge storage due to saturated operation of the npn transistors and by their comparatively long storage time constant in the upward-injecting mode. Also, the current capability of the pnp current source is limited by high-level injection and by practical design compromises needed in order to integrate both pnp and npn transistors with the same set of processes. Moreover, the signal swing in the worst case is well beyond the minimum required to define the logic levels. This article discloses a circuit configuration which extends the speed capability to a large degree with very little penalty in area.

A schematic of a standard MTL gate is shown in Fig. 1. A pnp transistor Q1 connects a voltage source Vp to npn transistors Q2A-Q2C. A logic input signal is applied to node B, and output signals are generated on collectors C1-C3.

The new circuit configuration is shown in Fig. 2. It is tailored for relatively high speed, and hence operates at a relatively high current level. In this circuit, a resistor, Rp, is used with a power-supply voltage, Vp, to supply a current of any practical magnitude. Resistor Rp can be implemented by a polysilicon film resistor or as a diffused resistor. Either approach has little impact on the processes needed for the rest of the gate, requiring little extra silicon area at high gate current.

In Fig. 2, an npn transistor Q3 is used in addition to output transistors Q2D- Q2F. Transistor Q3 has its base 1 shorted to its collector 2. Device Q3 serves to control the saturation of output transistors Q2D-Q2F, and thus minimizes the charge storage. By proper choice of the relative collector areas the transistors can be designed to adequately sink the worst-case source current, Ip, yet avoiding heavy saturation. To see that this is so, note that all four transistors have the same base-to-emitter voltage (assuming negligible r(BB)'s and r(EE)'s), and hence have the same emitter current density when not saturated.

Let I(E3) designate the emitter current of Q3 and A(3) its intrinsic base- emitter area, and let I(E,J) designate the emitter current of an output npn and A its intrinslc bas...