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Double Speed, Single Precision Vector Register Organization Using Double Port Chips

IP.com Disclosure Number: IPCOM000051696D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 4 page(s) / 134K

Publishing Venue

IBM

Related People

Brantley, WC: AUTHOR [+2]

Abstract

This article describes a vector register organization that allows single-precision operands to be fetched and stored twice as fast as double-precision operands. A vector processor usually has a pipelined arithmet unit which is capable of producing one double-precision result per machine cycle. With small added complexity the unit can be modified to produce two single-precision results per machine cycle.

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Double Speed, Single Precision Vector Register Organization Using Double Port Chips

This article describes a vector register organization that allows single- precision operands to be fetched and stored twice as fast as double-precision operands. A vector processor usually has a pipelined arithmet unit which is capable of producing one double-precision result per machine cycle. With small added complexity the unit can be modified to produce two single-precision results per machine cycle.

The described vector register organization supports double-speed, single- precision vector operations. Consider a two-address vector architecture where the two addresses specify the source and destination registers. The source and destination vector registers must each be capable of supplying two single- precision operands per cycle. The destination register must, in addition, be capable of absorbing two single-precision operands per cycle.

The vector registers are composed of stacks of double-port memory chips. The width of the memory chip is assumed to be a submultiple of the size of a single-precision number so that an integral number of memory chips can be paralleled to form each stack. The stacks are made from double-port register chips which allow one element to be read and one element to be written per cycle. Thus, one element being read prevents any other element from being read from the same stack.

A register organization is a binding of (register number, element number, and bit field) of the registers to (stack number, address, and bit field) of the stacks. Register organizations are shown graphically. In the conventional organization in Fig. 1, the symbols have the following meanings: Fr[e]b is a floating point vector register where

the register number is r (=0,2,4,6),

the element number is e (=0,1,2,...,E-1), and

the bit field is b (=[0:63] or any subset,

M=[32:63] L=[0:31]).

In the conventional organization single-precision operands can be accessed only at the rate of the double-precision operands. For example, is some is a double-precision operation, F0[0]LM and F2[0]LM are read and sent to the functional unit each cycle. On each successive cycle the next pair of elements is put into the functional unit. If P is the pipeline length in cycles, then F2[0]LM emerges from the pipelined is a single precision operation carried out at double speed, two elements, c and c+1, are read both F0 and F2 and sent to the functional unit: F0[c]L, F0[c+1]L, F2[c-P]L) F2[c-P+1]L) are written into F0[c-P]L and F0[c-P+1]L, respectively.

Shown in Fig. 2 is a register organization which supports double-speed, single-precision operation. The key to its double-speed operations is that even and odd elements of a register are word-swapped. That i...