Browse Prior Art Database

Zero Power and Gate

IP.com Disclosure Number: IPCOM000051705D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Kraft, WR: AUTHOR [+4]

Abstract

A logic gate is described that absorbs no power.

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Zero Power and Gate

A logic gate is described that absorbs no power.

In the prior art, the use of transfer gates, as in Fig. 1, is a recognized technique to multiplex multiple signals into a register or into a load where charge trapping on the output is not a concern. As long as only one gate G1-GN is positive and the others grounded or held at a low potential, the selected transistor T1-TN will pass the data on nodes D1-DN. Capacitor Cs is the parasitic load capacitor present on the output node, which represents an unsatisfactory characteristic of this circuit. The output node forms a dot-OR circuit, so a transfer gate multiplexer may be viewed as an N-way AND-OR circuit.

As already pointed out, there is charge trapping on capacitor Cs. If, however, a depletion-mode transistor is interposed from node OUT to ground, as shown in Fig. 2, a bleeder path is formed to ground, dissipating the charge on capacitor Cs. This allows the use of the transfer gate circuit as a zero power And gate viewed again as an N-way AND-OR circuit.

Multiple inputs may be realized, as shown in Fig. 3. Here, both gates, as well as input D3, have to be positive before the OUT line goes positive.

These circuits have a characteristic that the output is a threshold voltage down from the lowest amplitude gate, unless the gate voltage amplitudes are large enough to be a threshold above the input amplitude.

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