Browse Prior Art Database

Dense Hot Electron Programmable Memory

IP.com Disclosure Number: IPCOM000051737D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 79K

Publishing Venue

IBM

Related People

Gaffney, DP: AUTHOR [+5]

Abstract

A programmable read-only memory is provided having an array operable at relatively low voltages wherein each cell has a heavily doped ion-implanted N+ region under a thin oxide layer to utilize a small capacitor which tracks with the active device capacitor. In the array, four cells share a common contact and polysilicon lines are provided to guard against recessed oxide breakdown. By adding an erase tab extending from the floating gate, the cell can be made to operate in an electrically erasable programmable read-only memory.

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Dense Hot Electron Programmable Memory

A programmable read-only memory is provided having an array operable at relatively low voltages wherein each cell has a heavily doped ion-implanted N+ region under a thin oxide layer to utilize a small capacitor which tracks with the active device capacitor. In the array, four cells share a common contact and polysilicon lines are provided to guard against recessed oxide breakdown. By adding an erase tab extending from the floating gate, the cell can be made to operate in an electrically erasable programmable read-only memory.

As illustrated in Figs. 1 and 2, with Fig. 1 being a plan view of the cell and Fig. 2 being a sectional view taken through Fig. 1 at line 2-2, the cell includes a semiconductor substrate 10 having recessed oxide regions 12, a word line formed as an N+ diffusion 14, and a thin oxide layer having a first segment 16 formed over word line diffusion 14 and a second segment 18 formed over a transistor channel region 20. First and second doped polysilicon lines 22 and 24 having first and second insulating layers 26 and 28, respectively, are provided to guard against breakdown of the recessed oxide regions 12 at word line diffusion
14. A floating gate 30, which is also preferably made of doped polysilicon material, is disposed over the first and second thin oxide segments 16 and 18. A pair of diffusions 32 and 34, forming source and drain regions, are provided on opposite sides of the floating gate 30, as seen...