Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Staggered Control Pulse Generator

IP.com Disclosure Number: IPCOM000051767D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Enright, CJ: AUTHOR

Abstract

Some serial storage memories, such as those implemented with CCD (charge) coupled device) technology, require the generation of staggered timing pulses, as shown in Fig. 1.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Staggered Control Pulse Generator

Some serial storage memories, such as those implemented with CCD (charge) coupled device) technology, require the generation of staggered timing pulses, as shown in Fig. 1.

The pulses of Fig. 1 can be produced without segmented delay lines and with less cost and improved accuracy by the combination of a counter and a decoder, as shown in Fig. 2. Four-bit binary counter 1 receives clock pulses on line 2 and provides the sequence of output pulses A, B, C, D of Fig. 3 on the designated lines of Fig. 2 in a conventional manner.

Outputs A and B are not used. Outputs C and D are applied to a two input- four output decoder 3 which generates the desired staggered pulse sequence P1, P2, P3 and p4 of Fig. 1 on the designated lines. The ""down'' portions of output Pl are generated while inputs C and D are both ""down'', output P2 is generated while C is ""up'' and D is ""down'', and so on, as can be seen by inspection of the waveforms.

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]