Browse Prior Art Database

High Performance, Low Power Voltage Doubler

IP.com Disclosure Number: IPCOM000051773D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Arzubi, L: AUTHOR [+4]

Abstract

As an application example of an improved bootstrap configuration, a voltage doubler is disclosed which, in comparison with those known in the art, offers advantages with respect to performance, power dissipation, and layout (density).

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High Performance, Low Power Voltage Doubler

As an application example of an improved bootstrap configuration, a voltage doubler is disclosed which, in comparison with those known in the art, offers advantages with respect to performance, power dissipation, and layout (density).

A typical problem encountered with the design of FET circuits, particularly dynamic memory arrays, is the generation of control pulses which temporarily exceed the supply voltage VH, the highest voltage in the system, by more than the threshold voltage VT. This is desirable because the full VH value is required, for example, for restoring the array bit lines.

The approach used in the art to generate such pulses is shown in Fig. 1. Pulse phi 2 sets the initial conditions: Transistors 1 and 3 ON, nodes C and B grounded, nodes A and D on VH - VT. Upon its appearance, phi 1 precharges the load as well as C1 via transistor 1. Then, the gate of transistor 1 as well as the gate of transistor 3 are discharged, and transistor 2 is free to bootstrap, allowing VCL to be doubled via VC1. phi 2 restores the initial conditions.

Problems encountered in this circuit are: . Transistor 1 is very large, since it has to charge CL and C1. . Transistor 2 dissipates much power, while its source is kept down and its gate is charged. . Transistor 3 is very large, since it is expected to hold the source of transistor 2 to ground, while its gate is charged. . C1, by being charged and discharged each cycle, leads to unnecessary power dissipation. . The performance of transistor 2 (load driver) is limited by the rise time of its source, so that the performance during bootstrapping is poor.

A circuit which avoids all these problems and still uses the same phases is shown in Fig. 2. In this circuit, the initial conditions are set via phi 2. Nodes A, B, D, E, K are grounded. Nodes F and L are charged to VH, node H is charged to VH - VT. When phi 1 appears, CL is charged to VH via transistor 1, and the gate of transistor 12 is charged to VH via transistor 16, while its source is kept grounded. C1 is charged once via transistor 6 and never discharged. When node C is discharged via transistor 18 to a value below VT, node E is free to rise. Transistor 12 bootstraps shorting nodes E and F, and C2, precharged via transistor 11, bootstr...