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Browse Prior Art Database

Dual Entry Point Gas Panel Data Loading

IP.com Disclosure Number: IPCOM000051783D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Pearson, KA: AUTHOR [+2]

Abstract

Operation of a plasma display panel device consists of a data loading time, an execution time for writing or erasing, and a normalization time following the write or erase during which the affected cells become stabilized. In practice, the times for these events are unequal since the serial data load to the matrix driver modules takes longer than the normalization time between write cycles. The serial organization results from the practical constraints of limited I/0 pins on integrated driver modules, limitations of the large-scale integrated circuitry in general. By way of example, 32 circuit driver modules may operate at a 3 MHz data rate, but the number of bits to be loaded in one scan line is sufficiently large that the loading time exceeds the normalization time.

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Dual Entry Point Gas Panel Data Loading

Operation of a plasma display panel device consists of a data loading time, an execution time for writing or erasing, and a normalization time following the write or erase during which the affected cells become stabilized. In practice, the times for these events are unequal since the serial data load to the matrix driver modules takes longer than the normalization time between write cycles. The serial organization results from the practical constraints of limited I/0 pins on integrated driver modules, limitations of the large-scale integrated circuitry in general. By way of example, 32 circuit driver modules may operate at a 3 MHz data rate, but the number of bits to be loaded in one scan line is sufficiently large that the loading time exceeds the normalization time. Since the logic is working near its peak utilization rate, another means must be devised to increase the loading rate.

Referring to Fig. 1, which illustrates a logic system for addressing a plasma display device, the data is applied on line 11 to a logic input circuit, designated AND/OR block 13. The output data from logic element 13 is sequentially applied and temporarily stored in a buffer comprising shift registers 15, 17, 19, 21. By using a 6 MHz input data rate, pairs of registers in the input buffer, such as 15, 17, are loaded sequentially followed by the loading of the second pair of shift registers 19, 21. The 6 MHz data clock input on line 23 is converted to a 3 MHz signal by 32-bit counter 25 and appears on line 27. Also, the counter provides control to AND/OR unit 13 such that at the end of the 32nd data clock, the data is steered to the next shift register. The 32-bit driver modules adapted for driving 32 individual lines in the plasma display device are also connect...