Browse Prior Art Database

Bit Line Selection Circuit for Programming Level Voltages in an Electrically Alterable Read Only Storage

IP.com Disclosure Number: IPCOM000051800D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 80K

Publishing Venue

IBM

Related People

Tien, PC: AUTHOR

Abstract

A bit line selection circuit uses low level (5-volt) dynamic logic gating on the memory array for selectively routing programming level voltages and thereby avoids the transmission of programming level voltages through the bit line decoder where a voltage-initiated device breakdown might occur. 0n the array, the nodes subjected to high voltage may be protected using a ring of metallization to prevent breakdown.

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Bit Line Selection Circuit for Programming Level Voltages in an Electrically Alterable Read Only Storage

A bit line selection circuit uses low level (5-volt) dynamic logic gating on the memory array for selectively routing programming level voltages and thereby avoids the transmission of programming level voltages through the bit line decoder where a voltage-initiated device breakdown might occur. 0n the array, the nodes subjected to high voltage may be protected using a ring of metallization to prevent breakdown.

Referring to Fig. 1, the usual method for providing programming conditions at the bit line is to precharge the gate of the output transistor t(o) of the read/write circuit 12 while applying a programming level voltage signal í(P) at the drain of transistor t(o). The signal í(P) causes a bootstrapping effect via the capacitor C
(B) to charge the node Y(P) to the programming voltage level. Concurrently, programming level voltage is routed through the bit line decoder 14, causing the bit line node Y(b) to be charged to the programming voltage level.

Now referring to Fig. 2 and Fig. 3, a programming operation using the subject circuit proceeds as follows:

Signal CSN turns off all internally generated clocks, restores the chip, and discharges bit line Y(j) and node N(p). Clock signals í(1) and í(2) trigger operation of the bit line decoder 14 and word line decoder 20 to turn on transistors T(B) and T(S). Then clock signal í(3) charges the selected bit l...