Browse Prior Art Database

Adder Architecture

IP.com Disclosure Number: IPCOM000051805D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 82K

Publishing Venue

IBM

Related People

Williams, TA: AUTHOR

Abstract

Adder architecture is disclosed having a reduced computation time for two additions of three binary operands. A pair of adjacent bits from adjacent positions in each of three binary operands are input to a pair of one-bit carry save adders whose outputs are cascaded into a two-bit carry propagate adder with a carry look-ahead feature. The resultant operation of two additions of three operands can be carried out for a single-addition-equivalent delay time of approximately one-third the delay time of a conventional one-bit carry propagate adder.

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Adder Architecture

Adder architecture is disclosed having a reduced computation time for two additions of three binary operands. A pair of adjacent bits from adjacent positions in each of three binary operands are input to a pair of one-bit carry save adders whose outputs are cascaded into a two-bit carry propagate adder with a carry look-ahead feature. The resultant operation of two additions of three operands can be carried out for a single-addition-equivalent delay time of approximately one-third the delay time of a conventional one-bit carry propagate adder.

In Fig. 1, a prior-art 14-bit adder with a simple ripple carry propagate network is shown. For single addition of the 14-bit operand A with the 14-bit operand B, each corresponding bit pair A(i), B(i) is input through a gate G to a simple one-bit binary adder FA having a third input Ci for the carry of the next lower order bit position. The carry Ci output from the binary adder in each respective bit position is input as the carry Ci+1 to the input of the binary adder in the next higher order bit position. The sum output E(i) is passed through the driver D at each respective bit position. A one-unit time delay is incurred at every gate G and every driver D, and a two-unit time delay is incurred at every adder element FA. Since the delay incurred at each stage in passing through the respective gates G occurs simultaneously, the gates G impose but a single delay unit to the overall time delay of the circuit. However, since the carry output from each adder FA must be input to each respective next higher-order adder before the addition operation is completed, a full 28-unit delay interval will be incurred before a valid sum bit E13 is output from the l4th adder FA.

Each driver D also imposes a one-unit time delay each of which sequentially occurs as valid outputs become sequentially available from consecutively higher-order adders FA so that in effect, the single delay unit for the driver D at the 13th bit position is the only significant delay in the overall operation arising from the drivers D. The resultant overall delay in the operation of the adder in Fig. 1 is then 30 delay units in length for a single addition of two binary operands A and B.

Fig. 2 shows another prior-art approach to the single addition of two binary operands, where a two-bit carry propagate adder D/FA(C) having a carry look- ahead feature, is substituted for a corresponding pair of one-bit carry propagate adders FA, as shown in Fig. 1. The two bit carry propagate adder with carry look-ahead feature executes the binary addition of two corresponding pa...