Browse Prior Art Database

Common Storage Accessing for Multiple Microprocessor System

IP.com Disclosure Number: IPCOM000051818D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Rust, LM: AUTHOR

Abstract

A system having multiple microprocessor subsystems 1, 2, 3 (Fig. 1) accesses a common storage 4 over data and address busses 41, 42 whenever this storage is selected by a dot-OR control line 43. To avoid contention for storage cycles, each subsystem 1, 2, 3 uses interconnected enable outputs EN and inhibit inputs IN1, IN2 to enforce a priority hierarchy.

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Common Storage Accessing for Multiple Microprocessor System

A system having multiple microprocessor subsystems 1, 2, 3 (Fig. 1) accesses a common storage 4 over data and address busses 41, 42 whenever this storage is selected by a dot-OR control line 43.

To avoid contention for storage cycles, each subsystem 1, 2, 3 uses interconnected enable outputs EN and inhibit inputs IN1, IN2 to enforce a priority hierarchy.

Each subsystem such as 1 (Fig. 2) includes a microprocessor 11 having data and address busses 111, 112 and a control line REQ which requests a storage cycle. Completion of a cycle is positively signalled back to processor 11 by the CMP input. The data bus contains one line specifying whether this cycle is to be a read cycle or a write cycle. A private storage 12 occupies part of the address range of bus 112, indicated by a low level on line AR phi, which may be merely a high-order bit of bus 112. Gates 13 are enabled to transmit the data and address signals to the common storage for a high level on AR phi when priority logic 14 determines that subsystem 1 has priority for a common-storage cycle. Logic 14 also generates the COM signal for initiating a common-storage cycle.

Storage logic 14 (Fig. 3) generates a private-storage select signal PRV whenever AND gate 141 detects a storage cycle request REQ and AR phi=phi indicates that the address is in the range contained in private store 12. (T1, T2, and T3 are conventional cycle-timing signals.) PRV remains...