Browse Prior Art Database

Patch Circuits for Read Only Storage

IP.com Disclosure Number: IPCOM000051819D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Regehr, JL: AUTHOR [+2]

Abstract

Incorrect data in the read-only storage (ROS) of a microprocessor system is patched by detecting the addresses of data blocks to be changed, inhibiting the normal ROS, and outputting modified data from another ROS. The address-detection circuits also specify multiple patch lengths and provide several options for increasing the address range of the patch capability.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 67% of the total text.

Page 1 of 2

Patch Circuits for Read Only Storage

Incorrect data in the read-only storage (ROS) of a microprocessor system is patched by detecting the addresses of data blocks to be changed, inhibiting the normal ROS, and outputting modified data from another ROS. The address- detection circuits also specify multiple patch lengths and provide several options for increasing the address range of the patch capability.

Patch subsystem 10 receives microprocessor ROS address bus 11 and separates it into several groups of lines. The low-order four lines 12 directly control the low-order addresses of a 1K-word data ROS 20 in order to specify one of sixteen 16-bit words in a particular patch to be returned as microprocessor data 21. Translation ROS 30, having 1K bytes, converts a ten-bit group 13 of address lines 13 into a six-bit patch number 31, which selects one of 64 different patches stored in ROS 20.

The two remaining bits 32 and 33 specify whether lines 31 represent no patch address at all (D6D7=00), an eight-word patch from addresses XXX8 to XXXF (when D6D7=01), an eight-word patch from addresses XXX0 to XXX7 (when D6D7=10), or a full 16-word patch from XXX0 to XXXF (when D6D7=11). Select logic 40 uses A12, D6 and D7 to produce a signal 41 for inhibiting the normal ROS and enabling patch-data ROS 20 for the appropriate addresses.

Range logic 50 uses a high-order address line 14 to provide several selectable options for specifying the addresses of the patches. When switch 51 is...