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Alterable Patch Circuits for Read Only Storage

IP.com Disclosure Number: IPCOM000051820D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Regehr, JL: AUTHOR

Abstract

Incorrect data in the read-only storage (ROS) of a microprocessor syste is patched by detecting the addresses of data blocks to be changed, inhibiting the normal ROS, and outputting modified data from another memory. Both this other data memory and the address-detection memory are random-access (read/write) memory (RAM) loadable from an I/O bus of the microprocessor system.

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Alterable Patch Circuits for Read Only Storage

Incorrect data in the read-only storage (ROS) of a microprocessor syste is patched by detecting the addresses of data blocks to be changed, inhibiting the normal ROS, and outputting modified data from another memory. Both this other data memory and the address-detection memory are random-access (read/write) memory (RAM) loadable from an I/O bus of the microprocessor system.

Patch subsystem 10 receives microprocessor ROS address bus 11 and separates it into several groups of lines. The low-order lines 12 directly control the low-order addresses of a 1K-word data RAM 20 in order to specify one of sixteen 16-bit words in a particular patch to be returned as microprocessor data
21. Translation RAM 30, having 1K bytes, converts a ten-bit group of address lines into a six-bit patch number 31. RAM bits 32, 33 specify whether or not lines 31 represent a valid patch number. Control logic 40 uses the D06, D07 signals on lines 32, 33 to produce signals 41, 42 for inhibiting the normal ROS and enabling patch-data RAM 20 for the appropriate addresses.

Control logic 40 also allows RAMs 20, 30 to be loaded with variable data from the microprocessor's input/output (I/O) data bus 14, for purposes such as system development or initial program loading from a diskette or other I/O device. When the system receives a power-on reset signal 15, control logic detects a particular block of I/O addresses on bus 16 and produces a signal 43 to s...