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Data Reordering for Read Backward Operations

IP.com Disclosure Number: IPCOM000051826D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Ziecina, FJ: AUTHOR

Abstract

In computer systems, data read from input/output devices, such as a tap drive, is entered into a buffer before being transferred to either the central processing unit or storage via the channel. Some computer systems, because of the storage interface, require that the data be sent to the channel in ascending address order even when the data being transferred resulted from a read backward operation of an input/output device. Because of this, it is necessary to reorder the data, and this can be done either as the data is entered into or removed from the buffer. In either instance an address counter specifies the location in the buffer being accessed. Thus, it is necessary for the address counter to generate two address sequences, one for forward and one for backward reading.

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Data Reordering for Read Backward Operations

In computer systems, data read from input/output devices, such as a tap drive, is entered into a buffer before being transferred to either the central processing unit or storage via the channel. Some computer systems, because of the storage interface, require that the data be sent to the channel in ascending address order even when the data being transferred resulted from a read backward operation of an input/output device. Because of this, it is necessary to reorder the data, and this can be done either as the data is entered into or removed from the buffer. In either instance an address counter specifies the location in the buffer being accessed. Thus, it is necessary for the address counter to generate two address sequences, one for forward and one for backward reading.

In Fig. 1, address counter 10 consists of N stages where the outputs from the two low-order stages are applied to exclusive-OR circuits 15 which also have an input from read backward latch 20, whereby if this latch is set, the two low- order bits are inverted. This provides the proper address sequence for reordering the data. When latch 20 is not set, exclusive-OR circuits 15 have no effect, and the output of counter 10 is decoded in the normal counting sequence which is used when data does not have to be reordered.

A slightly different implementation is shown in Fig. 2 where the set output of latch 20 is used to condition AND circuits 26 and 27 to p...