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# Augmented Digital to Analog Converter

IP.com Disclosure Number: IPCOM000051850D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 31K

IBM

## Related People

Laczko, L: AUTHOR

## Abstract

An augmented digital-to-analog converter (DAC) is described which responds to the logical inputs in such a way that the output is increased or decreased with the value represented by the logical input.

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Augmented Digital to Analog Converter

An augmented digital-to-analog converter (DAC) is described which responds to the logical inputs in such a way that the output is increased or decreased with the value represented by the logical input.

Fig. 1 shows an example wherein a conventional 8-bit DAC reference input = 1 volt. The second most significant logical input or bit has a value of 25% of the reference. (When the second most significant bit is turned on, the DAC output will be 0.25 x 1V = 0.25V.

In Fig. 2, the same conditions apply to the positively augmented DAC. When the second most significant bit is turned on, the output will be increased by 25% and the output voltage will be 1V + (O.25 x 1V) 1.25V.

In Fig. 3, the same conditions apply to the negatively augmented DAC. When the second most significant bit is turned on, the output will be decreased by 25%, and the output voltage will be 1V -(0.25 x 1V) = 0.75V.

The circuit for the positively augmented DAC comprises a DAC and a summing amplifier, as in Fig. 4. The summing amplifier receives the reference voltage Vr on one input. The other input receives the reference voltage multiplied by the DAC's Gain = Vr x A. The output is equal to the algebraic sum of the two inputs.

The circuit for the negatively augmented DAC comprises a DAC and a difference amplifier, as shown in Fig. 5. The difference amplifier receives the reference voltage Vr on one input. The other input receives the reference voltage multiplied by...