Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Interface Testing

IP.com Disclosure Number: IPCOM000051867D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Sutherland, RG: AUTHOR [+3]

Abstract

The advent of the writable PLA (Programmable Logic Array) provides the opportunity to built test systems that are easily adaptable to various I/O interfaces and to test factors that are time variant.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Interface Testing

The advent of the writable PLA (Programmable Logic Array) provides the opportunity to built test systems that are easily adaptable to various I/O interfaces and to test factors that are time variant.

This article discusses a system designed to test UNIT CHECK (error) conditions injected into system controller interfaces and where the subsequent sense data is replaced by the test system. Examples of actual test cases for three different interfaces will be discussed along with a design description for a ""sense-forcing'' device for achieving fast, efficient, repeatable testing of microcoded ERPs (Error Recovery Procedures).

To efficiently test ERPs, it is necessary to control the type and number of errors given to the microcode under test, reproducing error conditions where microcode failure/repair is involved. The speed and adaptability of PLAs are able to meet these requirements and still remain flexible enough to adapt to the different interfaces with minimal impact, i.e., applied to different interfaces in a minimal time.

The interface tester is adapted to have an interface section interposed between a CPU or other programmable unit and its controlled units, such as a programmed control unit. Other interface sections represented by the small circles can be inserted between a control unit and its controlled devices. The interface section consists of gates which selectively interpose a so-called force section into the interface which causes certain signal lines to be blocked or forced, i.e., exterior data insertion. The tag and bus lines are taken from the interface section into the force section, or in PLA's perform logical functions for error injection and diagnostic purposes. The PLAs in the force section are programmable through a loader and a monitor section which can provide logging functions. The loader can be actuated directly from the CPU or from a separate maintenance processor. The loader, the monitor, and the force section all consist of PLAs.

The force section consists of writable PLAs that are personalized to the interface to receive error injection. These PLAs are also loaded with pertinent control information, such as types of errors, number of retries, desired conditions for error injection i.e., command to be injected, etc. The inputs and outp...