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IP.com Disclosure Number: IPCOM000051883D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Gheewala, TR: AUTHOR

Abstract

This article relates to a two-interferometer DC flip-flop with wide margins. The circuit alleviates the ""hang-up'' problem of the loop-latch by employing an additional gate in series with the gate current.

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This article relates to a two-interferometer DC flip-flop with wide margins. The circuit alleviates the ""hang-up'' problem of the loop-latch by employing an additional gate in series with the gate current.

This flip-flop is identified as a ""sloop'' flip-flop because it contains an additional gate in series with the gate current of the storage loop, as shown in Fig. 1. In Fig. 1, when a SET signal is applied, it switches interferometer D2 and transfers the gate current I(DC) to the parallel inductor L, thus storing a ""1''. The damping resistor Rd and the non-latching load resistor R(NL) are selected to minimize of interferometer D(2). To RESET the flip-flop, a control current is applied to both D(1) and D(2). Assume that the flip-flop is storing a ""1''. 0n application of the RESET pulse, interferometer D(1) switches to the voltage state and starts steering the gate current into the load resistor R(NL). The current is pulled out from the interferometer D(2) (Fig. 2), setting up a circulating current in the loop. But, when the current through the interferometer D2 exceeds the threshold current in the presence of the RESET pulse, it switches D2 and dissipates the flux stored in the loop. When the RESET pulse is removed, the interferometer D(1) resets because the load resistor R(NL) is so chosen as to make D(1) nonlatching. The gate current once again flows through D(1) and D(2), and the flip-flop is reset.

If two or more RESET pulses are applied consecutively, there is a danger that every time interferometer D2 switches, some current may be transferred to the inductor. This could reduce the gate current and the output margins. One way to solve this problem is to use the circuit arrangement of Fig. 3. This circuit does not allow a RESET pulse to follow another RESET pulse since the T* input on AND gate 10 will be ""0'' if the last input was a RESET pulse. Another way would be to...