Browse Prior Art Database

Risking and Falling Edge Expansible Digital Debounce Circuit

IP.com Disclosure Number: IPCOM000051904D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Kroeger, WL: AUTHOR

Abstract

This digital debounce circuit utilizing a series of D flip-flops and a pair of inverters is expansible to produce any required debounce time on both the rising and falling edge of a signal.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Risking and Falling Edge Expansible Digital Debounce Circuit

This digital debounce circuit utilizing a series of D flip-flops and a pair of inverters is expansible to produce any required debounce time on both the rising and falling edge of a signal.

Fig. 1 shows a logic diagram of the debounce circuit in its general form. The circuit is expansible by providing more D flip-flops connected as shown. The debounce time is determined by purely digital components according to the following equation: Debounce time = (N-1) over F where N = number of D-off stages, and F = frequency of the input clock.

Fig. 2 shows the timing waveform for a six-stage version of the generalized circuit of Fig. 1. Note that the input falling edge is delayed from its last bounce to the output, edge A, by the debounce time or five clock periods. The rising edge of the input is not delayed, but is transferred immediately to the output, edge B. This provides for a quick return of one of the two edges of the output without sacrificing debounce on either edge. It will be noted that the rising edge of the input has the same bounce protection as the falling edge.

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]