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Preliminary Synchronization of Controlled Data Link Between a Processor and a Controlled Tool

IP.com Disclosure Number: IPCOM000051905D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Baker, DC: AUTHOR [+2]

Abstract

The interface between the processor and the controlled tool limited distance controller (LDC) provided by the output shown in the figure is controlled by an advanced data link controller (ADLC). During normal operation, the LDC receive clock is self-synchronizing; i.e., the transitions indicative of the change in plurality of the binary data are also utilized to self-synchronize the controller. Since such transitions in the binary data cause synchronization, the present expedient proposes that a preliminary synchronization expedient be provided before the real data comes across; i.e., upon an indication that data is coming, the predetermined synchronization sequence passes through the LDC having a predetermined number of transitions which will synchronize the LDC receive clock before the true data comes across.

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Preliminary Synchronization of Controlled Data Link Between a Processor and a Controlled Tool

The interface between the processor and the controlled tool limited distance controller (LDC) provided by the output shown in the figure is controlled by an advanced data link controller (ADLC). During normal operation, the LDC receive clock is self-synchronizing; i.e., the transitions indicative of the change in plurality of the binary data are also utilized to self-synchronize the controller. Since such transitions in the binary data cause synchronization, the present expedient proposes that a preliminary synchronization expedient be provided before the real data comes across; i.e., upon an indication that data is coming, the predetermined synchronization sequence passes through the LDC having a predetermined number of transitions which will synchronize the LDC receive clock before the true data comes across.

The preliminary synchronization will be described with respect to the figure. When request to send (RTS) has been issued and the command Clear To Send (CLRSND) has been received from the limited distance controller (LDC), the SYNC latch 11 is added on to thereby remove the low CLRSND' reset to the ripple counter 10. On the next rising transmitter clock (TXCLK) pulse to latch 11, the ripple counter 10 begins counting. The low bit output of the ripple counter 10 is used to drive the send data (SNDATA) signal through the preframe bit sync (PFBS) gate 17. With each tr...