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Cell Design for Masterslice Logic Chips

IP.com Disclosure Number: IPCOM000051913D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 78K

Publishing Venue

IBM

Related People

Carpenter, LC: AUTHOR [+6]

Abstract

This masterslice cell design has first level metal lines passing direct over active devices formed in a silicon substrate, permitting direct contact of the lines to the inputs or outputs in the active devices. This cell design is particularly useful for manufacturing Schottky transistor-transistor logic (TTL) cells. Improved wirability and density is achieved with automatic wiring programs.

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Cell Design for Masterslice Logic Chips

This masterslice cell design has first level metal lines passing direct over active devices formed in a silicon substrate, permitting direct contact of the lines to the inputs or outputs in the active devices. This cell design is particularly useful for manufacturing Schottky transistor-transistor logic (TTL) cells. Improved wirability and density is achieved with automatic wiring programs.

Regions in a silicon substrate or chip used to form active devices in logic circuits or gates are illustrated, e.g. at 48 in IBM Technical Disclosure Bulletin 23, 115-117 (June 1980). A circuit or gate which may be formed in these regions is illustrated in Fig. 1 as a conventional TTL cell. This cell has an input transistor T1 with four input emitters E1, E2, E3 and E4 and a Schottky diode 10 connected between its base B and collector C, an output transistor T2 with a Schottky diode 12 connected between its base b and collector c and first, second and third resistors R1, R2 and R3.

As shown in Fig. 2, which illustrates substantially only one gate or circuit in a chip, this TTL circuit is formed between a voltage supply line V1 or Vcc and a ground line GND in an N type epitaxial layer 11. Disposed within layer 11 is input transistor T1 having an N+ subcollector 13, a P type base 14 formed in layer 11 and emitters E1, E2, E3 and E4 formed in base 14. A P+ isolation region 16 extending below N+ subcollector 13 and into the P- type silicon substrate surrounds input transistor T1 and a reach-through located at C extends from the surface of the chip to N+ subcollector 13.

Also, disposed within layer 11 is output transistor T2 having an N+ subcollector 18, a P type base 20 formed in layer 11 and an emitter e formed in base 20. The P+ isolation region 16 also surrounds output transistor T2 and a reach-through located at c extends from the surface of the chip to N+ subcollector 18.

The first resistor Rl includes diffusion regions 22 and 24 having different P+ concentrations disposed in layer 11 and is connected to a first common contact
26. The second resistor R2 includes diffusio...